library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MEM_MAPPED_IO is
	
	PORT (
	CLK : in STD_LOGIC;
	
	DATA_IN : in STD_LOGIC_VECTOR(31 downto 0);
	ADDR_IN : in STD_LOGIC_VECTOR(0 downto 0); -- Res1, Res0
	ENABLE : in STD_LOGIC;
	WRITE_ENABLE : in STD_LOGIC;
	RES1 : out STD_LOGIC_VECTOR(31 downto 0);
	RES2 : out STD_LOGIC_VECTOR(31 downto 0)
	
	);
	

end MEM_MAPPED_IO;

architecture Behavioral of MEM_MAPPED_IO is
begin
	process(clk)
	begin
		
		if (clk'event and clk = '1') then
		
			if (write_enable = '1' and enable = '1') then
		
				if (addr_in = "0") then
					res1 <= data_in;
				else
					res2 <= data_in;
				end if;
				
			end if;
		end if;
	
	
	end process;

end Behavioral;

